Protel Design System Design Rule Check
PCB File : C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Date     : 2022/11/21
Time     : 22:54:09

Processing Rule : Clearance Constraint (Gap=6mil) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All)
Rule Violations :0

Processing Rule : Routing Layers(All)
Rule Violations :0

Processing Rule : Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All)
Rule Violations :0

Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil)  and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:01