diff --git a/History/PCIE_Brige_PCB.~(49).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(49).PcbDoc.Zip new file mode 100644 index 0000000..1d7a354 Binary files /dev/null and b/History/PCIE_Brige_PCB.~(49).PcbDoc.Zip differ diff --git a/History/PCIE_Brige_PCB.~(50).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(50).PcbDoc.Zip new file mode 100644 index 0000000..2340222 Binary files /dev/null and b/History/PCIE_Brige_PCB.~(50).PcbDoc.Zip differ diff --git a/History/PCIE_Brige_PCB.~(51).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(51).PcbDoc.Zip new file mode 100644 index 0000000..5020aa3 Binary files /dev/null and b/History/PCIE_Brige_PCB.~(51).PcbDoc.Zip differ diff --git a/History/PCIE_Brige_PCB.~(52).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(52).PcbDoc.Zip new file mode 100644 index 0000000..03befc5 Binary files /dev/null and b/History/PCIE_Brige_PCB.~(52).PcbDoc.Zip differ diff --git a/History/PCIE_Brige_PCB.~(53).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(53).PcbDoc.Zip new file mode 100644 index 0000000..b3f9ec4 Binary files /dev/null and b/History/PCIE_Brige_PCB.~(53).PcbDoc.Zip differ diff --git a/History/PCIE_Brige_PCB.~(54).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(54).PcbDoc.Zip new file mode 100644 index 0000000..56677e5 Binary files /dev/null and b/History/PCIE_Brige_PCB.~(54).PcbDoc.Zip differ diff --git a/History/PCIE_Brige_PCB.~(55).PcbDoc.Zip b/History/PCIE_Brige_PCB.~(55).PcbDoc.Zip new file mode 100644 index 0000000..e0d51ca Binary files /dev/null and b/History/PCIE_Brige_PCB.~(55).PcbDoc.Zip differ diff --git a/PCIE_Brige_PCB.PcbDoc b/PCIE_Brige_PCB.PcbDoc index f17a29c..2ad347a 100644 Binary files a/PCIE_Brige_PCB.PcbDoc and b/PCIE_Brige_PCB.PcbDoc differ diff --git a/Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.drc b/Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.drc new file mode 100644 index 0000000..70d4876 --- /dev/null +++ b/Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.drc @@ -0,0 +1,36 @@ +Protel Design System Design Rule Check +PCB File : C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc +Date : 2022/11/21 +Time : 22:54:09 + +Processing Rule : Clearance Constraint (Gap=6mil) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All) +Rule Violations :0 + +Processing Rule : Routing Layers(All) +Rule Violations :0 + +Processing Rule : Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All) +Rule Violations :0 + +Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil) and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) +Rule Violations :0 + + +Violations Detected : 0 +Waived Violations : 0 +Time Elapsed : 00:00:01 \ No newline at end of file diff --git a/Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.html b/Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.html new file mode 100644 index 0000000..0b70bd7 --- /dev/null +++ b/Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.html @@ -0,0 +1,308 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

+ + + +
+ + + + + + + + + + + + + + + + + + + + + +
Date:2022/11/21
Time:22:54:09
Elapsed Time:00:00:01
Filename:C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
+		 + + + + + + + + + +
Warnings:0
Rule Violations:0
+

Summary

 + + + + + + + + +
WarningsCount
Total0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Rule ViolationsCount
Clearance Constraint (Gap=6mil) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All)0
Routing Layers(All)0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All)0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil) and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All)0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)0
Total0

+